P. Maurer's Website, DGL, FHDL, Education, Research
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Peter M. Maurer
Technical Reports
| Design Automation | Computer Architecture | Software Testing | Referencing the Reports |
Click Here to read and comment on more recent reports.
How to Reference These Technical Reports.
Proper reference is for the report "DA-22 1989 THE FHDL ROM TOOLS" is:
P. Maurer, Z. Wang, C. Morency, The FHDL ROM Tools, Department of Computer Science, Technical Report Number DA-22, Baylor University, Waco, TX, 76798, 1989.
A number of these technical reports have been published, usually after extensive revision. In most cases, when a technical report has been published, references should be made to the published work rather than to the technical report.
Design Automation
Referencing the ReportsClick on the report number to download.
| Number | Title |
| DA-1 1991 | GATEWAYS: A TECHNIQUE FOR ADDING EVENT-DRIVEN BEHAVIOR TO COMPILED UNIT-DELAY SIMULATIONS |
| DA-2 1990 | DYNAMIC FUNCTIONAL TESTING FOR VLSI CIRCUITS |
| DA-3 1989 | THE FLORIDA HARDWARE DESIGN LANGUAGE |
| DA-4 1991 | USING GATEWAYS WITH LEVELIZED COMPILED SIMULATION |
| DA-5 1989 | HDL DRIVEN CHIP LAYOUT WITHIN THE FHDL DESIGN FRAMEWORK |
| DA-6 1990 | MDCSIM: A COMPILED EVENT-DRIVEN MULTI-DELAY SIMULATOR |
| DA-7 1991 | TWO NEW TECHNIQUES FOR COMPILED MULTI-DELAY SIMULATION |
| DA-8 1989 | TECHNIQUES FOR MULTI-LEVEL COMPILED SIMULATION |
| DA-9 1990 | OPTIMIZATION OF THE PARALLEL TECHNIQUE FOR COMPILED UNIT-DELAY SIMULATION |
| DA-10 1990 | AUTOMATIC ROUTING OF INTEGRATED CIRCUIT CONNECTIONS: A TUTORIAL |
| DA-11 1991 | THE SHADOW ALGORITHM: A SCHEDULING TECHNIQUE FOR BOTH COMPILED AND INTERPRETED SIMULATION |
| DA-12 1988 | SCHEDULING HIGH-LEVEL BLOCKS FOR FUNCTIONAL SIMULATION |
| DA-13 1988 | THE COMPLEXITY OF DETECTING SYMMETRIC FUNCTIONS |
| DA-14 1991 | COMPILED UNIT-DELAY SIMULATION FOR CYCLIC CIRCUITS |
| DA-15 1989 | TECHNIQUES FOR UNIT-DELAY COMPILED SIMULATION |
| DA-16 1991 | TWO NEW TECHNIQUES FOR UNIT-DELAY COMPILED SIMULATION |
| DA-17 1990 | COMPILED UNIT-DELAY SIMULATION FOR CYCLIC CIRCUITS |
| DA-18 1989 | THE FHDL MACRO PROCESSOR |
| DA-19 1988 | COSIM: AN EXPERIMENTAL CONCURRENT FAULT SIMULATOR |
| DA-20 1989 | LECSIM: A LEVELIZED EVENT DRIVEN COMPILED LOGIC SIMULATOR |
| DA-21 1989 | THE FHDL PLA TOOLS |
| DA-22 1989 | THE FHDL ROM TOOLS |
| DA-23 1991 | SCHEDULING BLOCKS FOR HIERARCHICAL COMPILED SIMULATION |
| DA-24 1995 | IS COMPILED SIMULATION REALLY FASTER THAN INTERPRETED SIMULATION? |
| DA-25 1995 | THE INVERSION ALGORITHM FOR DIGITAL SIMULATION |
| DA-26 1995 | PARALLEL MULTI-DELAY SIMULATION |
| DA-27 1995 | THREE-VALUED SIMULATION WITH THE INVERSION ALGORITHM |
| DA-28 1995 | UNIT DELAY SCHEDULING FOR THE INVERSION ALGORITHM |
| DA-29 1995 | FANOUT FREE BLOCKS AND MULTI-DELAY LOGIC SIMULATION |
| DA-30 1995 | MDCSIM: A COMPILED EVENT-DRIVEN MULTI-DELAY SIMULATOR |
| DA-31 1995 | THE FHDL MANUAL |
| DA-32 1998 | PACKED INPUT VECTOR SIMULATION WITH THE INVERSION ALGORITHM |
| DA-33 1998 | LOGIC SIMULATION WITH INTERLOCKED STATE MACHINES |
Software for the FHDL system is available.
Experimental simulators implementing many of the algorithms described in the tech reports are also available.
Computer Architecture
Referencing the ReportsClick on the report number to download.
| Number | Title |
| CA-1 1995 | SAM: A Multithreaded Pipeline Architecture for Dataflow Computing |
| CA-2 1995 | Strategies for Implementing a Multithreaded Shared Pipeline Processor |
| CA-3 1995 | A Multithreading Architecture with Multiple Independent Shared Pipelines |
| CA-4 1995 | MAPPING THE DATA FLOW MODEL OF COMPUTATION INTO AN ENHANCED VON NEUMANN PROCESSOR |
| CA-5 1995 | Appendix A. A Sample program for Matrix Multiplication |
Software Testing
Referencing the ReportsClick on the report number to download.
| Number | Title |
| SE-1 1991 | THE DESIGN AND IMPLEMENTATION OF A GRAMMAR-BASED DATA GENERATOR |
| SE-2 1990 | Generating Test Data with Enhanced Context Free Grammars |
| SE-3 1995 | THE DGL MANUAL |
| SE-4 1995 | DGL Grammars are Universal |
The DGL Software is also available.
Education
Referencing the ReportsClick on the report number to download.
| Number | Title |
| ED-1 1997 | Design Automation Principles: An Essential Part of an Engineer's Education |
| ED-2 1997 | Enhancing the Design Experience for Computer Engineers |
| ED-3 1997 | You Can Try This at Home: Visual Programming in Engineering Education |
Problems
Report any problems, complements, or comments to Peter M. Maurer at
Email: peter_maurer@baylor.edu
Phone: (254) 710-7305
Fax: (254) 710-3889
Address:
-- Department of Computer Science
-- Box 97356
-- Baylor University
-- Waco, TX 76798-7356
-- USA.
Peter M. Maurer's home page.