Prof. Peter M. Maurer's Biography
Please note that this biography tends to be out of date most of the time.
- B.A. in Mathematics -- St.
Benedict's College, Atchison, Kansas, 1969
- M.S. in Computer Science -- Iowa
State University, Ames, Iowa, 1979
- Ph.D. in Computer Science -- Iowa
State University, Ames, Iowa, 1982.
- Currently he is an associate professor of
- From 1987-2002 he was an associate professor of
Computer Science and
Engineering and member of The Center for
Microelectronics Research at the
University of South Florida,
- From 1982-1987 he was a Member of
Technical Staff at Bell Laboratories Holmdel, where he
participated in the design and testing of several VLSI
chips. He was primarily responsible for the design
verification and testing of the WE 32108 floating point
accelerator, which never failed to divide correctly. He
also designed several tools to assist in the verification
and testing of the WE 32100 CPU, and the WE 32101 Memory
- From 1973-1978 he worked for the
State of Iowa as a professional computer programmer, and
- From 1969-1972 he was in the United
States Army, where he worked as a computer programmer,
and some-times North Vietnamese Interpreter/Translator
- After graduating from high school
in 1965 (Boone, Iowa) he was a college student, and an
occasional construction worker.
- VLSI Design Automation
- Component-Level Programming
- Metamorphic Programming
- Random Software Testing
- Computer Architecture
- VLSI Design
- Parallel Processing
- Author of the FHDL hardware design
language and simulation system
- Author of the popular test-data
generation tool DGL.
- IEEE Computer Society
- Phi-Kappa-Phi honor society.
- American Legion
- Peace Lutheran Church, Hewitt TX.
- “Component Level Programming,”
Prentice Hall, 2003, ISBN 013045804X.
Papers (Not Comprehensive)
Event-Driven Simulation by Exploiting the Output Observability of Gate
Clusters,” IEEE Transactions on CAD, to appear Nov 2003.
“What If They Gave a Revolution and Nobody Came?” Computer, June 2000.
“The Inversion Algorithm for Digital Simulation” IEEE Transactions on Computer
Aided Design, July 1997.
with Y. Lee) “The Multi-Delay Parallel Algorithm,” IEEE Transactions on
Computer Aided Design, Dec 1996.
(with Y. Lee)
“Gateways: A Technique for Adding Event-Driven Behavior To Compiled
Simulations”, IEEE Transactions on Computer Aided Design, Vol 13, No. 3, Mar.
1994, pp. 338-352.
“The Shadow Algorithm: A Scheduling Technique for both Compiled and
Interpreted Simulation ,” IEEE Transactions on Computer Aided Design, vol 12,
No. 9, Sept. 1993, pp.1411-1413.
and Implementation of a Grammar-based Data Generator," Software Practice and
Experience, Vol. 22, No. 3, March 1992, pp. 223-244.
"Two New Techniques for Unit-Delay Compiled Simulation," IEEE Transactions on
Computer Aided Design, Vol 11, No. 9, Sept 1992, pp. 1120-1130.
Blocks for Hierarchical Compiled Simulation," IEEE Transactions on CAD,
Vol. 10, No. 2, Feb. 1991, pp. 184-192.
Test Data with Enhanced Context Free Grammars," IEEE Software, Vol. 7,
No. 4, July, 1990, pp. 50-56.
Functional Testing for VLSI Circuits," IEEE Design & Test of Computers,
Vol. 7, No. 6, Dec. 1990, pp. 42-49.
(With A. D. Schapira) "A Logic-to-Logic Comparator for VLSI Layout
Verification," IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems, Vol. 7, No. 8, pp.897-907, Aug 1988.
"The Design Verification of the WE 32106 Math Accellerator Unit," IEEE Design
and Test of Computers, June 1988, pp. 11-21.
Rose is a Rose ...," The American Mathematical Monthly, Vol. 94, No. 7,
Aug.-Sept. 1987, pp. 631-645.
(with A. E.
Oldehoeft) "The use of Combinators in Translating a Purely Functional Language
into Low-Level Data Flow Graphs," Computer Languages, Vol. 8, No. 1, 1983, pp.
(with S. Kondapuram)
“Random Characterization of Design Automation Algorithms,” IEEE Annual
Symposium on VLSI, Feb 2003.
(with Khalid Hamzan)
“Using a Relational Database System to Implement Object Oriented Databases,”
Proceedings SCI 2002.
(with Khalid Hamzan) “A
Data Implementation Scheme for Mapping Objects to Relational Databases,”
Proceedings SCI 2001, pp. 438-443.
(with W. Schilp) “The
Three-Valued Inversion Algorithm,” 13th International Conference on
VLSI Design, Jan. 2000.
Based Simulation of Digital Circuits,” European Design Automation and TEst
conference, Mar. 2000.
(with M. R. Varanasi)
“Interactive Logic Design on the World Wide Web,” European Workshop on VLSI
Education, May 2000.
“Event Driven Simulation
Without Loops or Conditionals,” ICCAD 2000, Nov. 2000.
for Hierarchical and Partitioned Circuits,” 12th International
Conference on VLSI Design, Jan. 1999.
“Software Bit-Slicing: A
Technique for Improving Simulation Performance,” European Design Automation
and TEst conference, Mar. 1999.
(With M. Varanasi, S.
Katkoori, W. Mak) “Component Level Programming: A Revolution in Technology,”
FIE ’99, Nov. 1999.
“Enhancing The Design
Experience for Computer Engineers,” FIE ’98, Nov. 1998.
Automation: An Essential Part of a Computer Engineer’s Education,” FIE ’98,
(With N. Ranganathan and
M. Varanasi) “A Model for a Computer Engineering Program,” FIE ’98, Nov. 1998.
(with W. Schilp) “The
Unit-Delay Inversion Algorithm,” ICCAD-96.
“Is Compiled Simulation
Really Faster than Interpreted Simulation?” International Conference on VLSI
“The Inversion Algorithm
for Digital Simulation,” Proceedings of the International Conference on
Computer Aided Design, 1994.
(with Y. Lee) “Parallel
Multi-Delay Simulation,” Proceedings of the International Conference on
Computer Aided Design, 1993, pp. 759-762.
(with Y. Lee) “Two New
Techniques for Compiled Multi-Delay Simulation,” Proceedings of Southeastcon
92, pp. 175-179.
(with Y. Lee) “Compiled
Unit-Delay Simulation For Cyclic Circuits,” Proceedings of Southeastcon 92,
(with Y. Lee) “Two New
Techniques for Compiled Multi-delay Simulation,” Proceedings of 29th DAC,
June, 1992, pp. 420-423. (Not a duplicate
"Optimization of the
Parallel Technique for Unit-Delay Compiled Simulation," Proceedings of ICCAD
1990, pp. 70-73.
(with Z. Wang) "LECSIM:
A Levelized Event Driven Compiled Logic Simulator," Proceedings of the 27th
Annual Design Automation Conference, 1990, pp. 491-496.
(with Z. Wang)
"Techniques for Unit-Delay Compiled Simulation," Proceedings of the 27th
Annual Design Automation Conference, 1990, pp. 480-484.
"Automatic Routing of
Circuit Connections: A Tutorial," Proceedings ICC-90, pp. 801-805.
"The FHDL Macro
Processor," Proceedings of the 28th Annual ACM Southeast Regional
Conference, pp. 10-17.
(with C. Morency), "The
FHDL PLA Tools," Proceedings of the 28th Annual ACM Southeast Regional
Conference, pp. 3-9.
(with C. Morency), "The
FHDL ROM Tools," Proceedings of the 28th Annual ACM Southeast Regional
Conference, pp. 18-24.
(with Z. Wang, C.
Morency, A. Tokuta and
"The Florida Hardware Design Language," Proceedings Southeastcon-90,
(with N. Bhate and A.
Tokuta) "Development of Schematic Capture Support for FHDL," Proceedings
Southeastcon-90, pp. 442-446.
(with C. Morency) "HDL
Driven Chip Layout within the FHDL Design Framework," Proceedings
Southeastcon-90, pp. 438-440.
(with C. Morency)
"Standard Cell Floorplanning within the FHDL Automatic Placement Tool,"
Proceedings Southeastcon-90, pp. 435-437.
(with Zhicheng Wang)
"Scheduling High-Level Blocks for Functional Simulation,"
Proceedings of the 26th Design Automation Conference, pp.
87-90, June, 1989.
(With Mayra N.
Hernandez) "COSIM: An Experimental Concurrent Fault Simulator," Proceedings
of the 27th Annual Southeast Regional ACM Conference, 1989, pp. 333-337.
"Mapping the Data Flow
Model of Computation onto an Enhanced von Neumann Processor," Proceedings of
the 1988 International Conference on Parallel Processing, pp. 235-239, 1988.
(with several others)
"An IEEE Standard Floating Point Chip," ISSCC-85 Digest of Papers, 1985, pp.
Grants (Not Comprehensive)
"Research in Compiled Logic simulation," NSF, $51,000, July 1990-July 1992.
“Improving the Speed of Logic Simulation,” NSF $163,000, July 1994-July 1997.
“Introducing Design and Design Automation Into the Undergraduate Curriculum,”
NSF $600,000, Sept 1995 - Sept. 1998. (CDA-9522265)
01/05/1999 System and method for digital simulation of an electrical circuit.
10/10/2000 System and method for digital simulation of an electrical circuit.
Languages (Not necessarily up to date)
German – Read and Speak well
French – Read well, Speak
Spanish – Read moderately well
Portuguese – Read moderately well
Italian – Read moderately well
Dutch – Read moderately well
Russian – Read with difficulty
Vietnamese – Read and speak with
Latin – So So.
Peter M. Maurer